Faradayic™ Process for Electronic Interconnect Fabrication
|Organization:||Faraday Technology Inc, 45315, US|
|I.P. Brief:||The Faradayic™ Process is a platform technology suite addressing electronic manufacturing at the integrated circuit, chip-scale/wafer-level package, and printed circuit board hierarchies. This technology is covered by fifteen issued US and foreign patents and additional patents pending. This patent estate includes apparatus and process technology.|
|Summary of I.P.:||The Faradayic™ Process is a patented platform technology for electronic interconnect manufacturing. The technology suite consists of robust electro deposition, electro etching (electro polishing), and lead-free solder processes.
Faraday has demonstrated a single step electrically mediated electrochemical copper deposition/planarization(electro polishing) process for integrated circuit, chip-scale/wafer-level package, and printed circuit board hierarchies. Note the bath does not contain the difficult to control brightners, levelers, and accelerators which contaminate the deposit, and are typically found in currently used processes.
Faraday has demonstrated an electrically mediated electro etching process for anisotropic through mask etching of lines and spaces and other detailed features. Faraday’s approach minimizes under cutting, thus enabling tighter designs for lines and spaces.
Faraday has demonstrated the feasibility of an electrically mediated electro deposition process for lead free solders. The Faradayic™ Process has the ability to control the grain size in the desired range of 1-8 microns, while minimizing or eliminating internal stresses, and producing a deposit with a matte finish, through controlled manipulation of the applied electric field.
|Patent:||6,878,259; 6,863,793; 6,827,833; 6,750,144; 6,652,727; 6,524,461; 6,319,384; 6,309,528; 6,303,014; 6,210,555; 6,203,684|
|Keywords:||Integrated circuit, interconnect, package, electrodeposit, electroetch, electropolish|
|Specific Market:||Semiconductor, chip-scale package, wafer-level package, printed circuit board|
|Market Size:||In 2002, the market for equipment and copper electro-deposition were $764 million (projected annual growth estimate of 30%) and $161 million (projected annual growth estimate of 25%), respectively. By 2006 - 2007, the combined market should approach $3 b|
|State of the Art:||Traditional electroplating processes have been widely implemented for all hierarchies (integrated circuit, chip-scale/wafer-level package, printed circuit board) within the electronics manufacturing industry (including semiconductors). These traditional processes use complex chemical formulations including brighteners, levelers accelerators and the like and direct current or pulse/pulse reverse electric fields. |
|Competition:||Chip makers and tool makers are beginning to file pulse/pulse reverse patents for filling and planarization of interconnects. The US Patent Office is citing Faraday patents as prior art against these patent applications and consequently, are identifying the Faradayic™ Process for electronic interconnect fabrication as an opportunity. |
|Figures of Merit:||Tunability of electric field process control; shifting process control from chemical mediation to electrical mediation; achieving desirable surface profiles in a single processing step via electric field waveform sequencing. Faraday’s issued patents cover the specific elements listed above.|
|Tech. Obstacles:||Limited resources require a concentrated focus on industry relevant challenges. The major obstacle which affects Faraday’s technical efforts is lack of knowledge of specific industry needs. Without this obstacle, Faraday could more rapidly develop a process library for a wide range of feature geometries and sizes for different applications.|
|Market Obstacles:||1. Establishing credibility with industry leaders who have not previously heard of Faraday.
2. Gaining access to state-of-the-art samples and obtaining analysis of processed samples in a timely manner. Overcoming this challenge would enable technical and commercial progress by helping to establish Faraday’s credibility.
3 Overcoming the “Not Invented Here” thought processes sometimes encountered within established industry R&D organizations.
4. Establishing two-way communication with the legal departments of industry leaders, who are not involved with or affected by the business strategy of the company.
5. Maintaining communication with inventors and innovators within industry leaders, who are prohibited from interacting with external companies.
|Patent Landscape:||Faraday’s eleven issued US patents have been cited more than fifty times, including patents issued to AMD, Applied Materials, IBM, Intel, LSI Logic, Novellus and others. These citations emphasize the emerging importance of the Faradayic™ Process as related to electronic interconnect fabrication. |
|Publications:||1. J. Sun, H. McCrabb, E.J. Taylor and M. Inman (2006), Electrically Mediated Microetching, Circuitree, March, pp 12-17.
2. Jong-Min Lee, Heather McCrabb, E. Jennings Taylor, Ron Carpio, Current Distribution for the Metallization of Resistive Wafer Substrates Under Controlled Geometric Variations, J. Electrochem.Soc., in press.
3. H. Garich, J. Sun, L. Gebhart, M. Inman, E.J. Taylor, T. Dalrymple, N. Emami, R. Smith, T. Berg, R. Thompson and W. Richards (2006), The Effect Of Plating Cell Configuration On The Quality Of Copper Deposit For Printed Circuit Boards, IPC, Anaheim, CA.
4. H. McCrabb, H. Garich, L. Gebhart, J.M. Lee, M. Inman and E.J. Taylor (2005) Electrochemical Processing for Semiconductors, Packaging and MEMS Devices, SEMICON West, July, San Francisco, CA.
5. E.J. Taylor, J. Sun, H. Dyar, L. Gebhart, A. Bonifas, J-M Lee, R. Carpio and M. Inman (2004), Electrochemical Processing to Meet the ITRS Roadmap, SEMICON West, July, San Francisco, CA.
|Research Team:||6 members with 50+ combined years of experience. Key players: E. Jennings Taylor, PhD/Patent Agent; Heather McCrabb, MS; Holly Garich, MS; Lawrence Gebhart, BSME; Maria Inman, PhD, Jong-Min Lee, PhD.|