Venue | Press Room | Subscribe | Site Map
TechConnect Summit 2006
Home | About the Summit | Program | Advisory Boards | About TechConnect

Producing Sponsor

TechConnect

Platinum Sponsor

Welsh & Katz, Ltd.

Gold Sponsor

ISTC International Science & Technology Center

Ventures Enabling Sponsor

Atomic Venture Partners

Press Sponsor

Business Wire

Partnering Sponsor

NSTI

Supporting Organizations

Boston University
Midwest Research University Network

Media Sponsors

(joint with Nanotech 2006) Nature
Science
R&D Magazine

Summit News

Event Contact

Jennifer Rocha
955 Massachusetts Ave. #313
Cambridge, MA 02139
Phone: (774) 249-8514

Fast and Efficient Generalized Galois Field Fixed Field Constant Multiplier

Organization:UMass Lowell, 01854, US
I.P. Brief:This invention is a method and hardware solution that addresses the demanding resource requirements in calculating Advanced Encryption Algorithm for data security. This technology significantly improves on the speed and performance of both hardware resources and software throughput when calculating the algorithm.
Summary of I.P.:Rijndael is chosen as the next generation of Advanced Encryption Algorithm standard for data security. Rijndael algorithm requires Galois Field (GF) fixed field constant multiplication which employs large, fixed arrays of look-up-tables and calculations. Implementations based on look-up-tables are optimized for speed but at the cost of additional logic resources. This approach causes degradation in the system performance and increase processing time substantially. From a hardware standpoint, the calculation requires a significant amount of both gates and space on a chip. This breakthrough invention is a process and hardware solution that helps to reduce the hardware resource requirements by a factor of 21 for calculating the GF fixed field constant multiplications without degrading performance. It also improves software throughput versus software-only implementations by factors ranging from 10 to over 3043 depending on the processor word size. The invention reduces the required number of gates (from ? 131,000 to ? 6,500), thereby requiring considerably less real estate and enabling the circuit to be incorporated as a component on a chip, it could be deployed wiith 8-bit to 64-bit processor word sizes.
Patent:Provisional Patent filed on 1-30-2006
Keywords:Advanced Encryption Algorithm, Data Security, Rijndael, Network Security, Internet Security, Cryptography, Chip, Homeland Security
Primary Industry:Security
Specific Market:Information Security and Chip Manufacturers
Market Size:The market projection for information security is projected at over $10 Billion for the US Market alone.
State of the Art:Rijndael algorithm requires system resources in doing complex multiplication that involves look-up-tables and calculations. Such implementations are optimized for speed but utilizes substantial logic resources. It downgrades system performance and increases processing time and requiring a significant amount of both gates and space on a chip.
Competition:Unknown
Figures of Merit:This is a disruptive technology by a factor of 21 times over current hardware solution, it improves software throughput versus software-only implementations by factors ranging from 10 to over 3043. It reduces the required number of gates (from ? 131,000 to ? 6,500)
Tech.  Obstacles:None that we are aware of.
Market Obstacles:1. Hardware manufacturers to re-design the makeup of the chip. 2. Rinjdael to reach market adoption.
Publications:Elbirt, C. Paar, \"An Instruction-Level Distributed Processor for Symmetric-Key Cryptography\", IEEE Transactions on Parallel and Distributed Systems, vol. 16, no. 5, pp. 468-480, May, 2005. A. Elbirt, W. Yip, B. Chetwynd, C. Paar, \"An FPGA-Based Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists\", IEEE Transactions on VLSI, vol. 9, no. 4, pp. 545, August, 2001. A. Elbirt, C. Paar, \"An FPGA Implementation and Performance Evaluation of the Serpent Block Cipher\", Eighth ACM International Symposium on Field-Programmable Gate Arrays, Monterey, California, February 10-11, 2000 http://citeseer.ifi.unizh.ch/554474.html NTRU in Constrained Devices by D. Bailey, D. Coffin, A. Elbirt, J. Silverman, A. Woodbury
Research Team:Adam Elbirt, Christo Parr with over 25 years of experience in this research.

 

Home | About the Summit | Program | Advisory Boards | About TechConnect
Terms of use | Privacy policy | Contact | TechConnect Home
© 2005 TechConnect. All rights reserved.