H. Miyamoto, C. Ma, H. Tanoue, Y. Tanimoto, H. Kikuchihara, H.J. Mattausch, M. Miura-Mattausch
Hiroshima University, Japan
pp. 303 - 309
Keywords: compact model, CMOS circuit simulation, long-term degradation modeling, negative bias temperature instability, trap density
[Introduction] Prediction methods of long-term degradation of both p- and n-type metal oxide semiconductor field effect transistors (MOSFETs) in CMOS circuits is proposed. During CMOS circuit degradation, not all the MOSFETs but only several MOSFETs degrade crucially. Therefore it is required to detect the most degraded MOSFET suffered from given circuit operation condition at given degradation time. The developed methods can be utilized for this purpose and enable the optimization on circuit design for reliability. [Method] Different physical phenomena are responsible for the degradation of p- and n-MOSFETs. One is the negative bias temperature instability (NBTI) effect of p-MOSFETs and the other is the hot electron induced carrier trapping of n-MOSFETs. In our group both phenomena have been modeled for realizing CMOS circuit simulation. To apply the models in a practical commercial circuit, however, not only short-term degradation but also long-term degradation must be predicted. In this study we have developed the long-term NBTI effect model for p-MOSFETs and the long-term hot electron induced carrier trapping model for n-MOSFETs. An important advantage of the developed methods is the simplicity of the simulation with minimum simulation time while keeping the physically correct concept of the degradation mechanism. [Results and discussion] The developed simulation method for long-term degradation of circuits is investigated for the 3-stage ring oscillator circuit. The oscillation frequency degradation is simulated up to 1e8 seconds (10 years). This results shows that each values of degradation depends on the each condition in the circuit and developed model is applicable to detect the MOSFET critical for circuit performance.