Peking University Shenzhen SoC Key Lab., China
pp. 375 - 378
Keywords: nanometerT-FinFET, process technology, strain effect, performane enhancement, modeling
It is an often measure that the process-induced stress has been used in advanced CMOS process platform to increase the carrier mobility so to enhance MOSFET performance. It has also a strong effect on the mobility of T-FinFET once the kind of device is fabricated in the CMOS process platform as done always in experiment tunneling FET device. Here we report the proess-induced stress mobility enhance effect and developed a compact model for it, the layout dependence of the T-FinFET mobility due to process-induced stress is efficiently captured. The mobility model is verified for different layout dimensions for several stress-inducing process technologies through both process simulations and experimental data.