Santa Clara University, United States
pp. 210 - 213
Keywords: QCA, FFT, majority gate
Presenting novel designs for a Ripple Carry Adder, a Subtractor, and a Pipelined Array Multiplier using the Five-input Majority Gate (MAJ5) in Quantum-dor Cellular Automata (QCA). These designs are then used to implement the Fast Fourier Transform (FFT) Algorithm. The FFT implementation was previously introduced in 2012. However, it suffered from inefficiencies in terms of both area and speed, which are essential features for the aforementioned algorithm. The new designs are designed, optimized, and simulated using QCADesigner. It is shown that they indeed achieve higher levels of compactness and speed, due largely to the utilization of MAJ5, in addition to a new wire-crossing scheme suggested by another group. These building blocks are then used to optimize the FFT QCA implementation.