N. Lu, A. Baizley, X. Guan, J. Johnson, J. McCullen, A. Ozbek, A. Rahman, H. Wang, M. Yu, C. Zemke, W. Rausch, R. Wachnik
IBM, United States
pp. 293 - 299
Keywords: FinFET, process design kits (PDKs), local interconnect resistance model, diffusion resistance, parasitic resistance, 14nm technology
Parasitic resistance is a primary performance constraint in FinFET technologies. We report that new and innovative elements and features have been introduced into Process Design Kits for 14nm FinFET technology. They enable accurate and efficient modeling and simulations (i) of the effects of different contact schemes to local interconnects (LIs) on LI resistance and (ii) of the effects of shared, unshared, and merged diffusion regions on the performance of logic gates. These new elements and features aid circuit layout optimization. Measured 14nm data demonstrate the accuracy of the new modeling approach. New Element 1. LVS/PEX tools in IBM/GF 14nm SOI FinFET technology has been enhanced to netlist one of several MOL resistance models based on actual connection scheme to a given local interconnect. For LI layout commonly seen for drain, a specific LI resistance model lires_t is netlisted. For LI layout commonly seen for source, another specific LI resistance model lires_e is netlisted. Related layout information are passed to the LI models. New Element 2. A set of LI resistance models have been developed for 14nm FinFET technology and are used in the PEX flow. Each model handles one group of layout cases and only uses two nodes. Excellent model-hardware correspondence has been demonstrated. Simple two-node resistance models enable efficient circuit simulations. The inaccuracy of a pure PEX approach to model LI resistance will be discussed. New Element 3: For schematic simulations (e.g., using a single FinFET instance to represent a multi-finger FinFET), 14nm PDK provides schematic FinFET models that also include gate resistance, parasitic MOL and M1 resistance, and parasitic MOL capacitance elements associated with the multi-finger FinFET. RO switching delay can be easily simulated using a compact netlist that contains only pairs of FinFET instances to obtain RO delay as a function of fin number Nfin and/or finger number Nf. This enables efficient exploration of design choices by designers. There is a sweet spot (optimal fin number Nfin) for RO design. We explain this RO delay behavior. Measured data support that (Nfin•DCReff) and (Nfin•Ron) increase with Nfin at a constant NFET-PFET mean saturated Vt. New Element 4. A local interconnect in a diffusion region can be unshared or “shared and simultaneous switching”. This (layout + switching) difference has an impact on the actual resistance experienced by the drain current in the diffusion region and/or in the LI. LVS tool analyzes a layout and pass the information on shared vs. unshared to a netlisted lires model instance. Our early LI resistance models return a large resistance value for a shared LI. New Element 5. There are also two other (layout + switching) cases: stacked FET and “shared LI but non-simultaneous switching”. Our latest FinFET and LI models are stacked-FET based, and they correctly count the diffusion resistance values in all four (layout + switching) cases. Unshared LI based (FET + LI) models over-estimated the diffusion resistances in stacked FETs. The resulted under-estimation on FET’s drain current in the linear region was not negligible.