pp. 287 - 293
Keywords: FDSOI, compact modeling
Fully-Depleted Silicon-On-Insulator (FDSOI) technologies featuring Ultra-Thin silicon Body and Buried oxide (UTBB) have now entered into industrial production stage. These technologies present several decisive advantages over other options, such as excellent transistor electrostatic control, very low variability, simple planar process close to that of conventional bulk one, and very efficient back-bias effect. This latter feature allows a significant dynamic modulation of delay/power trade-off, which is a powerful know at circuit level. Therefore, to take full advantage of these technologies, circuit designer need compact models able to describe the transistor behavior over wide ranges of applied back biases, which actually requires considering FDSOI transistor as real Independent Double Gate (IDG) MOSFETs. In this paper, we will review the challenges that are to be addressed in order to build such compact models, from surface potential calculation to complete DC, AC and noise models. For each of these challenges, we will describe the original solutions specifically developed for Leti-UTSOI2, which is a complete and mature compact model, valid and predictive in all possible bias configurations of FDSOI transistors, and currently in use in industrial design kits.