University of Connecticut and Duke University Co-Develop Novel Screening Technique of Small Delay Defects

New methodology will detect SDDs and improve quality and reliability of semiconductor products
The research teams are using a much reduced pattern count in the chip testing process to detect small delay defects (SDDs). “By evaluating each test pattern according to its unique paths before applying the patterns to silicon, it allows the industry to select only high-quality patterns for testing. This will help to dramatically improve the quality of the test process and reduce the delay test costs while testers budgets,” notes Mohammad Tehranipoor, associate professor of Electrical and Computer Engineering, University of Connecticut, and Krishnendu Chakrabarty, professor of Electrical and Computer Engineering, Duke University. The research group is exploring ways to bring the technology to the commercialization phase. The chip testing process is being evaluated on silicon at Advanced Micro Devices, Inc. (AMD). The research was supported by the Semiconductor Research Foundation and the NSF.

↑ Back to TechConnect News™

Event Spotlights

DITAC
Austin, TX, December 1-3, 2015
DES
Austin, TX, December 1-3, 2015
 

Annual Meeting

TechConnect World 2015
Washington, DC, May 22-25, 2016